This invention relates generally to fault tolerant bubble memory design. More particularly, this application is related to an invention for a bubble memory design having additional minor loops in a major loop-minor loop field access design and a stationary register having the same number of positions as the total number of minor loops so that defective minor loops are internally identified in the memory.
In conventional manufacturing processes for bubble memory chips, a certain number of chips will prove to be defective and have to be discarded. Normal manufacturing control requires a certain trade-off between manufacturing 100% perfect devices and testing after the manufacturing process to discard or repair defective units. Obviously, defective memory chips cannot be repaired so the testing process must require that defective chips be discarded. Various designs in the prior art exist to increase the manufacturing process yield by designing bubble memory chips in such a way that a certain number of faults or defects may exists and yet have the chip usable in the particular bubble memory system. Many such fault tolerant designs exist employing both external logic and memory as well as various modifications of a standard chip design or combinations of both.
One system employing a modified chip design is shown in U.S. Pat. No. 3,921,156. In a normal major loop-minor loop field access memory design, the subject patent shows various bubble bypass circuits or loops in the system which may be semipermanently altered to eliminate defective minor loops. Such systems require comparatively complex bubble-bubble interactions on the memory chip in order to perform the path diversion logic functions and may be comparatively less reliable than certain externally performed logic functions.
Another concept involving alteration of magnetic paths from magnetic bubbles is shown in U.S. Pat. No. 3,990,058. However, the present application is based on major loop-minor loop organization rather than the alteration of paths in a serial memory. Furthermore, the present application does not involve alteration of magnetic bubble paths. U.S. Pat. No. 3,909,810 shows a scheme where extra minor loops are included in a bubble memory system and external memory sources are used together with logic devices to identify minor loops which are to be ignored in favor of the usable minor loops. Thus, all of the fault tolerance ability of the system shown in this patent is based on external logic devices while the memory chip differs from conventional memory chips only in that an excess number of minor loops are included on the chip in excess of the nominal capacity of the memory in order to allow for elimination of certain minor loops after testing. U.S. Pat. No. 4,073,012 shows a fault tolerant bubble memory which uses external logic and an external memory to contain faulty loop data.
U.S. Pat. No. 3,792,450 shows the use of a major loop-minor loop memory system having additional minor loops which are used for the purpose of containing a flaw table to identify the minor loop locations which are defective. This results in additional complexity to the memory in that additional connections and read gates are required to the memory chip to allow independent reading of the minor loop flaw tables. Further, care in design and construction of the system is required to insure than the proper synchronization is maintained between the minor loop and the remainder of the memory so that the correct correspondence is maintained in identity between indications of faulty minor loops and the actual faulty minor loops.
The present invention contains certain advantages in that synchronization of the flaw table is automatically constantly maintained with respect to faulty minor loop locations. Further, connections to the memory chip, according to the design of the invention, are not unnecessarily increased in that serial, merged reading of the stationary register and major loop is done by a common read gate. A further advantage of the present invention is that no separate or external memory device needs to be programmed with the fault information since that is designed into each individual memory chip.